Important Combinational Logic Circuits

1.0 Decoder

Translates an n-bit input codeword into a larger m-bit output word,

where m is 2^n

2. Multiplexer (MUX)

Connects one of 2^n input data lines to one output line.

3. Demultiplexer (DeMUX)

Connects one input data line to one of 2^n

output lines.

4. Read-Only Memory (ROM)

A programmable truth table with n-bit address input and (selects a row), m-bit data output (typically m = 8, for one row)

5. ROM Types

Decoder (selects a word)

Encoder array (encodes or stores the word)

Diode-fuse array

MOS transistor-fuse array

Double gate MOS transistor array

6. ROM implementations.

a. ROM (mask)

b. PROM (programmable ROM):

c. EPROM (erasable-programmable ROM):

d. EEPROM (electrically-erasable PROM):

e. Flash (fast block-based EEPROM)

7. Random Access Memory (RAM) is a Rewritable truth table of cells

8. SLC

SEQUENTIAL LOGIC CIRCUITS

Are logic circuits whose outputs dpend upon state.

8.FLIP-FLOPS (LATCH)

a circuit that has two stable states and can be used to store state information.

The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs.

9. Clocks

Outputs yield uniform rectangular waveforms when plotted against time.

Clock frequency = number of complete clock oscillations (cycles) per

second of time, expressed in Hertz or cycles per second (Hz=cycles/sec)

10 Ripple counter

a single JK-type flip-flop, with input fed from its own inverted output. This counter will increment once for every clock cycle

Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops

Synchronous counter – all state bits change under control of a single clock

Decade counter – counts through ten states per stage

Up/down counter – counts both up and down, under command of a control input

Ring counter – formed by a shift register with feedback connection in a ring

11. Data Transfer Modes

1. PARALLEL-IN/PARALLEL-OUT (PIPO)

2. SERIAL-IN/SERIAL-OUT (SISO)

3. PARALLEL-IN/SERIAL-OUT (PISO)

4. SERIAL-IN/PARALLEL-OUT (SIPO)

12.0 Data Latch Register

a register circuit capable of performing only PIPO data transfers.

13. Shift Register

register circuit capable of performing SISO data transfers.

14. Bidirectional shift registers

contain additional logic circuitry to support left or

right data shifts.